CMOS devices fabricated on silicon-on-insulator (SOI) substrates provide higher speed and consume less power. Similar to bulk silicon circuits, ESD protection is critical in circuit design and applications in order to achieve device reliability. Diode network structure techniques used in bulk silicon circuits for ESD protection, such as duo-diode, single diode or MVI (Mixed Voltage Interface) composed of diode string networks, are generally adopted for ESD protection in SOI circuits.
However, the buried oxide layer (BOX) in SOI circuits isolates device from substrate—a mechanism leading to ESD failure mode. Usually, ESD design generally adopts the form of a lateral diode such as the gated diode ESD protection device shown in FIG. 1. However, the lateral diode structure presents two major challenges. The first challenge is that the small junction area is vulnerable to defect, because of the heavy current density. These defects prohibit a device from releasing heavy current when needed, and eventually lead to ESD failure. However, attempts to enlarge the ESD diode junction area result in increased device domain area, making scaling difficult.
Chinese Patent Application No. 200910201331.0 (CN200910201331.0) tries to solve the problem of breaking-down of ESD protection diodes, by fabricating a diode spacer with an epitaxial layer to achieve the ESD protection effect of a traditional longitudinal diode in bulk silicon. Although the CN200910201331.0 design overcomes the junction defect problem, the spacer structure complicates the manufacturing process and reduces the device integration level, resulting in high overall cost.
Therefore, there is a need for a simpler and low cost ESD protection device for SOI integrated circuitry.